A resistive memory device, such as for example the electrically programmable resistive cross point memory device as described in US2003/0003674, is a non-volatile memory device which generally comprises an active layer capable of having its resistivity changed in response to an electrical signal, interposed between a plurality of conductive top and bottom electrodes. The active layer usually comprises a dielectric material, such as for example one or more metal oxide layers, a solid electrolyte material, a magnetic tunnel junction of a phase change material, which may be interposed between two conductive electrodes, for example wire-shaped Pt-electrodes. At a cross point of a top electrode and a bottom electrode, a cross point referring to each position where a top electrode crosses a bottom electrode, the active layer has a programmable region with a resistivity that can change in response to an applied voltage. The memory effect of the resistive memory device lies in the programming of the memory device into two distinct resistive states.
A resistive memory array, comprising a plurality of resistive memory elements, typically comprises a cross-bar array of top and bottom electrodes as illustrated schematically in FIG. 1, in top view in FIG. 2, and in cross-section in FIG. 3. The resistive memory device 1 comprises a plurality of top electrodes (e.g. word lines “WL”) and a plurality of bottom electrodes (e.g. bit lines “BL”) which, together with an active layer 2 between the top and bottom electrodes, form a plurality of cross-point memory elements. The active layer 2 is interposed between the plurality of word lines WL and bit lines BL. At each crossing of a word line WL with a bit line BL, a programmable region, i.e. a bit 3, is formed in the active layer 2. The resistivity of the bit 3 can be changed for example due to filament formation or filament disruption in response to a voltage or current applied between the corresponding word line WL and the bit line BL. The positions of the filaments are schematically indicated with closed circles 4 in FIG. 2. Supposing that the world lines WL and the bit lines BL each have a width F being the minimum width obtainable with a given technology, the density of the resistive memory device 1 as illustrated in FIG. 2 can be calculated to be 1 filament/4F2, thus 1 bit/4F2.
Such raw cross-point arrays with single RRAM elements lead to a large parasitic current flowing through non-selected memory cells. Hence raw cross-point arrays suffer from READ errors (sneak currents) and possibly from PROGRAM errors, as well as from excessive current and power consumption.
One solution to alleviate these problems is to put a selector 5 in each cell, as illustrated in FIG. 4. Ideally this can be a transistor, requiring the addition of another control word line 6, but also a (bipolar) diode/switch device has been proposed as a selector 5. Examples of resistive memory arrays comprising memory cells including selection transistors are given in US2009/014836.
Disadvantages of solutions including a selector 5 in each cell are the increase of the cell size, hence the reduced memory density, the more complex processing—not a simple cross-point array but requiring the definition of intermediate pillar elements—the fact that no appropriate two-terminal bipolar selector devices have been identified.
Accordingly, there is room for new structures and processing methods for manufacturing non-volatile memory cells, which allow a high cell density.